The fabrication of integrated circuits is an extremely complex process that may involve hundreds of individual operations. In view of the device and interconnect densities required in integrated circuits, it is imperative that the manufacturing processes be carried out with utmost precision and in a way that minimizes defects.
Yield analysis is performed in order to correct problems in manufacturing processes, and in order to plan, during the manufacturing phase, wafer starts appropriately. It is highly desirable to detect problems early in the design phase through yield analysis due to the multitude and complexity of process steps and their associated cost.
Currently, designers use yield prediction software to decide which design layout alternative will produce a better yield, and thus be printed, and to decide how many wafers to put inline, i.e., adjust the number of wafer starts for production per product based on real inline data to meet the yielding die commitments. Existing software for yield analysis, however, assumes that the likelihood of a defect to occur on different design elements is the same. In other words, design elements' contribution to causing defects is not substantially reflected in the existing yield analysis software.